1. Technical Field
The present invention relates to interconnect testing in electrical systems. More specifically, the present invention relates to interconnect testing using a hardware-based approach.
2. Description of Related Art
Traditional interconnect testing, like that described in Joint Test Action Group (JTAG) Institute of Electrical and Electronics Engineers (IEEE) standard 1149.1, has a strong dependence on software interaction and scan functions. IBM has expanded this single card testing concept in the original JTAG specification to multiple card testing within a system (Wire Test). The traditional Wire Test method involves scanning test patterns into the boundary latches of all chips in a system interface, sampling at all chips"" interfaces, and scanning the patterns out of each chip to compare the resulting patterns. This process is repeated so that every driver drives at least once in the system, with multiple patterns on each interface, to determine and diagnose problems such as shorts and opens on these interfaces, if they exist. In this manner, it can be determined if all interconnections between chips in a system are intact. Manufacturing and system assembly relies heavily on such patterns to test systems as they are built and to diagnose manufacturing problems.
The IBM eServer iSeries system, which in one model incorporates up to 164 processor chips and their associated memory and I/O controller support chips, has an order of magnitude more nets and chips connected over multiple cards than previous systems. This system has grown beyond the capabilities of the traditional system-wide Wire Test. More specifically, the time required to complete a software-driven test on a large system is unreasonable, as is the amount of pattern storage required by the traditional Wire Test methods.
Therefore, in light of the limitations of software-driven interconnect testing, a more hardware-driven test controlled by software would be desirable.
The present invention provides a method, program and system for electrical shorts testing. The invention comprises setting any chips to be tested to drive 0""s on their drive interfaces, and setting all receive interfaces on the chips to receive 0""s and log any failures. Next a single receive interface is selected for testing. A hardware shift register is associated with each drive side interface, wherein each bit of the register is connected to an off-chip driver on the interface. This hardware shift register for the selected interface is then set to all 0""s, and the first bit of the shift register is loaded to a 1. The invention then performs a pause count. After this count, the 1 is shifted to the next bit in the register and another pause count is performed. This process is repeated until the 1 is walked completely through the register and all pins on the interface have been tested. The walking 1 test is then repeated for any additional interfaces that require testing. Any nets not controlled by the new Electrical Shorts Test (EST) should ideally be set to drive 1 during this walking 1 test.
In addition, an inverted shorts test can be performed in which the 1 and 0 values are reversed and a walking 0 test is performed through the register, thus allowing the interfaces to be tested at both polarities. Nets not controlled by the new EST should be driven to 0 during the Inverted test.
Since the walking patterns are generated by the hardware at run-time, very little storage is required in the external service element that is controlling the running of these manufacturing testsxe2x80x94only the commands necessary to initialized the hardware, start the test on each interface and check for pass or fail of each interface. In addition, the EST runs very quickly, since the patterns are driven and checked across all bits on an entire interface after being set up and initiated by a small number of commands. The interface test itself (pattern generation and checking) occurs at a speed determined by bus clocks of the chips on the interface, not the speed of the JTAG test port and service element accessing that port. Therefore, the EST of the present invention is several orders of magnitude faster than traditional wiretest.